ProjectHardVERITESS – Erforschung neuartiger FPGA-Basisarchitekturen und deren Erprobung am Beispiel eines Datenloggers
Basic data
Acronym:
HardVERITESS
Title:
Erforschung neuartiger FPGA-Basisarchitekturen und deren Erprobung am Beispiel eines Datenloggers
Duration:
01/01/2013 to 28/02/2015
Keywords:
Datenlogger
Echtzeittest
verification
Überprüfung
Involved staff
Managers
Faculty of Science
University of Tübingen
University of Tübingen
Wilhelm Schickard Institute of Computer Science (WSI)
Department of Informatics, Faculty of Science
Department of Informatics, Faculty of Science
Local organizational units
Wilhelm Schickard Institute of Computer Science (WSI)
Department of Informatics
Faculty of Science
Faculty of Science
Funders
Berlin, Germany